Very Large Scale Integration (VLSI) of microelectronic devices and future downscaling of electronic systems require dielectric isolation to overcome problems associated with conventional junction isolation such as: latch-up, unscalable vertical dimensions, and increased leakage at elevated temperatures, see the artical by S. J. Duey and G. W. Neudeck, "A Novel Quasi-Dielectrically Isolated Bipolar Transistor Using Epitaxial Lateral Overgrowth", in J. Jopke, ed., Proceddings of the 1988 Bipolar Circuits & Technology Meeting, 1988, pp. 241-244. Methods to acieve this dielectric isolation are silicon-on-insulator (SOI) technologies. SOI technologies promise to offer increased device performance by reducing parasitic capacitance, interconnect delay, and increased radiation hardness. Many examples of SOI technologies are known, but with limited degrees of success and process maturity, for example, see the article by J. Jastrzebski, "Silicon on Insulators: Different Approaches: A Review", J. Crystal Growth, vol. 70, 1984, p. 253. In SOI technology, small islands of silicon which contain the individual device are fabricated on an insulating substrate, and then interconnected in the normal way. Likely to be attendant with these technologies is the difficulty, or inability to achieve "device quality" silicon on an insulating layer. Device quality is defined as silicon layers without crystallographic defects and/or impurities which prevent fabrication of functioning devices. One SOI technique employs the ion implantation of oxygen or nitrogen into bulk silicon forming a buried oxide (SiO.sub.2) called the SIMOX process, as described by M. K. El-Ghor, S. J. Pennycook, F. Namavar, and N. H., Karam in "Formation of Low Dislocation Density Silicon-on-Insulator by a Single Implantation and Annealing", Appl. Phys. Lett., vol. 57, 1990, p. 156, or a buried nitride (Si.sub.3 N.sub.4) layer. Other techniques relied on deposited amorphous or polycrystalline silicon on an amorphous substrate and then recrystallized by various techniques such as laser annealing, electron beam annealing and radiant heating. These methods did not achieve high quality devices and the techniques have been subsequently abandoned, note S. Wolf and R. N. Tauber's Silicon Processing for the VLSI Era, Vol. 1: Process Technology, Lattice Press, Sunset Beach, Calif., pp. 153-5. Epitaxial Lateral Overgrowth (ELO) is a method which employs the growth of an oxide layer on bulk silicon, and subsequent selective epitaxial growth from nucleation sites on bare silicon in patterned openings and subsequent overgrowth on the remaining oxide, see Duey et al., supra. A similar technique called Zone Melt Recrystallization (ZMR) uses a moving filament to remelt silicon deposited on SiO.sub.2 using patterned openings to the bulk Si below as a seed crystal for regrowth, note the article by G. A. Rozgonyi et al., "Structural and Electrical Properties of Epitaxial Si on Insulating Substrates", Appl. Phys. Lett., vol. 55, 1989, p. 586.
Another technology that has been investigated employs epitaxially grown silicon-on-sapphire (SOS). Early attempts at fabricating device quality SOS have been documented, for example, see G. W. Cullen's "The Preparation and Properties of Chemically Vapor Deposited Silicon on Sapphire and Spinel", J. Crystal Growth, vol. 9, 1971, p. 107 and F. P. Heiman and P. H. Robinson's "Silicon-On-Sapphire Epitaxial Bipolar Transistors", Solid State Electronics, vol. 11, 1968, p. 411. This latter reference achieved low gain functional transistors, but noted that small area devices must be fabricated because of the high density of crystal imperfections that cause emitter-collector shorts. Since then, techniques have been developed to improve the near interfacial region for thin silicon layers on sapphire such as Solid-Phase-Epitaxy (SPE), Double-Solid-Phase-Epitaxy (DSPE) and Solid-Phase-Epitaxy-And-Regrowth (SPEAR), see for example, the article by S. Lau et al., "Improvement of Crystalline Quality of Epitaxial Si Layers by Ion Implantation Techniques", Appl. Phys. Lett., Vol. 34, 1979, p. 76; G. A. Garcia and R. E. Reedy, "Electron Mobility within 100 nm of the Si/Sapphire Interface in Double-Solid-Phase Epitaxially Regrown SOS", Electronics Letters, Vol. 22, 1986, p. 537; and D. C. Mayer et al., "A Short-Channel CMOS/SOS Technology in Recrystallized 0.3 .mu.m-thick Silicon-on-Sapphire Films", IEEE Electron. Dev. Lett., Vol. EDL-5, 1984, p. 156. These techniques, however, do not provide device quality material for devices with more stringent materials requirements such as bipolar junction transistors, charge-coupled devices (CCDs), and others, requiring thicker films and high quality epitaxial layers, see L. Jastrzebski's "Origin and Control of Material Defects in Silicon VLSI Technologies: An Overview", IEEE Trans. Electron Dev., Vol. ED-29, 1982, p. 475. Previous attempts at fabrication of bipolar devices in SOS have been blocked by materials defects. The inability to achieve silicon epitaxially grown on sapphire without dislocations, slip planes, and twin defects results in a failure mechanism for devices by means of what is known as "diffusion pipes". Diffusion pipes are crystallographic defects which allow paths for dopant atoms to diffuse (or migrate) during high temperature anneals. The anneals are critical in the processing of semiconductor devices in that they allow the electrical activation of ion implanted dopant atoms. Therefore the diffusion of dopant from one junction into another (e.g. the emitter to the base) results in leaky or shorted devices. Therefore, research and development into high quality crystalline films on sapphire and novel processing techniques are of continuing interest for SOS device fabrication.
Laser processing of materials has been investigated for a variety of applications, and is being used in semiconductor processing of silicon VLSI in applications which range from laser-assisted etching, as referred to in S. D. Russell and D. A. Sexton's "Excimer Laser-Assisted Etching of Silicon Using Chloropentafluoroethane", in R. Rosenberg et al., In-Situ Patterning: Selective Area Deposition and Etching" Mater. Res. Soc. Proc., vol. 158, 1990, p. 325; chemical vapor deposition (CVD), as referred to by D. Lubben et al. in "Laser-Induced Plasmas for Primary Ion Deposition of Epitaxial Ge and Si Films", J. Vac. Sci. Technol., B, vol. 3, 1985, p. 968; and alloy formation, as referred to by J. R. Abelson et al. in "Epitaxial Ge.sub.x S.sub.i-x /Si (100) Structures Produced by Pulsed Laser Mixing of Evaporated Ge on Si (100) Substrates", Appl. Phys. Lett., vol. 52, 1988, p. 230, to name a few. Laser activation of ion implanted dopant has long been known as an alternative to conventional furnace annealing, see for example, A. E. Bell's "Review and Analysis of Laser Annealing", RCA Review, vol. 40, 1979, p. 295; and L. D. Hess et al. in "Applications of Laser Annealing in IC Fabrication"; in, J. Narayan et al., eds., Laser-Solid Interactions and Transient Thermal Processing of Materials, Mat. Res. Soc. Symp. Proc., vol. 13, 1983, p. 337; and techniques such as Gas Immersion Laser Doping (GILD) have proven valuable in the formation of shallow junctions in bulk silicon, note R. J. Pressley's "Gas Immersion Laser Diffusion (GILDing)", in C. C. Tang, ed., "Laser Processing of Semiconductor Devices", Proc. SPIE, vol. 385, 1983, p. 30.; and K. H. Weiner and T. W. Sigmon's "Thin-Base Bipolar Transistor Fabrication Using Gas Immersion Laser Doping", IEEE Electron Dev. Lett., vol. 10, 1989, p. 260. In addition, examination of excimer laser annealing of implant damage in bulk silicon has been demonstrated in the article by D. H. Lowndes et al., "Pulsed Excimer Laser (308 nm) Annealing of Ion Implanted Silicon and Solar Cell Fabrication", in J. Narayan et al., Laser-Solid Interactions and Transient Thermal Processing of Materials, Mat. Res. Soc. Symp. Proc., vol. 13, 1983, p. 407. These studies have, however, been limited to processing high quality bulk silicon, and have not explored the unique requirements of SOS.
Reports on laser processing SOS have not examined techniques required to solve materials problems for bipolar transistors and related demanding technologies. Yamada et al. performed thermally-assisted pulse laser annealing of SOS, see M. Yamada et al., "Thermally-Assisted Pulsed-Laser Annealing of SOS", in J. F. Gibbons et al., eds, Laser and Electron-Beam Solid Interactions and Materials Processing, Mat. Res. Soc. Symp. Proc., vol. 1, 1981, p. 503. Using Raman spectroscopy they measured the residual strain in annealed SOS due to the lattice mismatch between Si and sapphire. They performed no examination of laser dopant activation. Alestig et al. performed continuous wave (cw) laser annealing of ion implanted oxidized silicon layers on sapphire, see the article by G. Alestig et al., "CW Laser Annealing of Ion Implanted Oxidized Silicon Layers on Sapphire", in J Narayan et al., eds., Laser-Solid Interactions and Transient Thermal Processing of Materials, Mat. Res. Soc. Symp. Proc., vol. 13, 1983, p. 517. They demonstrated activation of boron and phosphorous dopants by illumination from both the top and backside of the wafer. They reported visible damage was obtained when using power sufficient to melt the silicon. Similarly, Hess et al. performed cw laser annealing of SOS to activate ion implanted dopant into MOS devices, see the article by L. D. Hess et al., "Laser-Assisted MOS/SOS Transistor Fabrication", in B. R. Appleton and G. K. Celler, eds., Laser and Electron-Beam Interactions with Solids, Mat. Res. Soc. Symp. Proc., vol. 4, 1982, p. 633. To prevent diffusion of dopant from the source or drain region into the gate region, the silicon was not melted to prevent spatial redistribution of the dopant. These references teach away from the use of melting SOS to prevent unwanted diffusion of dopant, and report decreased crystalline quality under these conditions.
Thus, a continuing need exists for a method of using a pulsed laser to perform a rapid melting of a select portion of a silicon island on sapphire, thereby diffusing dopant to electrically active sites without allowing time for undesirable diffusion along defect pipes to eliminate the problems associated with standard annealing techniques, to provide a uniform dopant profile desirable for bipolar bases, to effectively decouple the thermal activation of the emitter and base regions, and to provide for the advantage of fabricating functional devices in SOS material that has significant defects. The need further exists for such a technique that can be extended to fabrication of other semiconductor devices in SOS requiring activation of dopant atoms such as MOSFETs, CCDs, etc., and is amenable to process modifications to accommodate emerging materials, e.g. silicon-germanium alloys.